# BRHypervisor and xPC3200 E-cores **URL:** \ **Category:** HMI & Visualization\ **Tags:** apc-ppc, hypervisor\ **Created:** [July 17, 2025, 2:02pm UTC](https://community.br-automation.com/t/brhypervisor-and-xpc3200-e-cores/7683 "2025-07-17T14:02:41Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![Georg\_B](https://avatars.discourse-cdn.com/v4/letter/g/FF8800/32.png) [@Georg\_B](https://community.br-automation.com/u/Georg_B)\ **Post date:** [July 17, 2025, 2:02pm UTC](https://community.br-automation.com/t/brhypervisor-and-xpc3200-e-cores/7683/1 "2025-07-17T14:02:41Z")
BRHypervisor on Automation **PC 3200** - Efficient-Cores (E-cores) not usable. In a new installation on Automation **PC 3200** BRHypervisor uses no Efficient-Cores (E-cores) (Atom cores) in the GPOS (B&R Win10IoT2021). Only the two Performance-Cores (P-cores) are used. One by ARemb and the other by Windows. We can not find any option to configure that. There is no UEFI Update on the B&R-website at this time. Any ideas? Thank you in advance. ---
**Author:** ![kovarj](https://dub1.discourse-cdn.com/brcommunity/user_avatar/community.br-automation.com/kovarj/32/537_2.png) [@kovarj](https://community.br-automation.com/u/kovarj)\ **Post date:** [August 8, 2025, 1:44pm UTC](https://community.br-automation.com/t/brhypervisor-and-xpc3200-e-cores/7683/2 "2025-08-08T13:44:18Z")
Hi @Georg_B, since your topic has been open for a while and there is no reply from **BRCommunity** , can you please get in contact with first level support of your local B&R office and update us with your findings. Thanks, Jaroslav ---
**Author:** ![stephan.hatheuer](https://avatars.discourse-cdn.com/v4/letter/s/FF8800/32.png) [@stephan.hatheuer](https://community.br-automation.com/u/stephan.hatheuer)\ **Post date:** [August 12, 2025, 2:28pm UTC](https://community.br-automation.com/t/brhypervisor-and-xpc3200-e-cores/7683/3 "2025-08-12T14:28:22Z")
Dear Georg, the scenario described by yours, is fully right. APC/PPC3200 CPUs offer max. two performance cores. One is typically occupied by windows, the second one (if available, depending on CPU) is in case of hypervisor operation occupied by the hypervisor. The current version of hypervisor based on VX works from windriver is only support performance cores, this is also the reason why we cannot offer hypervisor in combination with APC/PPC3200 - celeron CPU. It is not possible to force either windows or hypervisor to use efficiency cores instead of performance cores. The use of efficiency cores is done automatically and B&R is not able to influence that procedure. As far as I’m having information from PG software VXworks is aware of this situation. Anyhow a roadmap for this issue to be solved is not available and not communicated. ---
**Author:** ![Georg\_B](https://avatars.discourse-cdn.com/v4/letter/g/FF8800/32.png) [@Georg\_B](https://community.br-automation.com/u/Georg_B)\ **Post date:** [August 18, 2025, 8:06am UTC](https://community.br-automation.com/t/brhypervisor-and-xpc3200-e-cores/7683/4 "2025-08-18T08:06:08Z")
Dear Stephan, This is really bad news as we were under the impression that the APC 3200 would be a major improvement in power. As we “loose” all the efficiency cores, when using hypervisor the APC 3200 is still notably faster as the APC 3100 but not as much as expected. Anyway thank you very much for the clarification! ---
**Author:** ![Georg\_B](https://avatars.discourse-cdn.com/v4/letter/g/FF8800/32.png) [@Georg\_B](https://community.br-automation.com/u/Georg_B)\ **Post date:** [August 21, 2025, 8:53am UTC](https://community.br-automation.com/t/brhypervisor-and-xpc3200-e-cores/7683/5 "2025-08-21T08:53:06Z")
Update: We got news from the support team. > Currently the hypervisor only supports the P cores, but Hypervisor support for E core and P core + HV support for cores assigned to the GPOS is in implementation. It is a non-goal of this version to assign the E cores also to the RTOS. > > This state is planned for release in **AR 6.4** on **2025-09-01**. > > In case of the 5APC3200.RPL1-000 you would have > > - **RTOS** : 1x P core with 1x logical cores > > - **GPOS** : 1x P core with 2x logical cores (HT) + 4x E cores with 4x logical cores (non HT) > > With **AS 6.5** it will be possible to assign the P+E cores individually to GPOS or RTOS if you need multiple cores in RTOS. So the problem could be fixed next month.