Innovation 2025 : Multicore Processing in Automation Software 6

[kovarj (Jaroslav Kovar)]

As modern hardware trends shift towards multi-core architectures, Automation Software 6 (AS6) has evolved to fully leverage these capabilities. This article outlines the technical implementation of multicore processing in AS6, its integration into runtime environments, and practical considerations for developers.

Why Multicore?

• CPU frequency has plateaued, and single-core performance improvements are marginal.
• Core counts are increasing, making parallel execution essential for performance gains.

AS6 adapts to this trend by enabling parallel task execution across multiple cores.

Runtime Architecture: From Single-Core to Multicore

Traditional Single-Core Execution

Tasks are queued and executed based on priority. Only one task runs at a time, limiting performance.

Multicore Execution Model

Tasks are distributed across available cores. Parallel execution of high-priority tasks is now possible. Dynamic load balancing ensures optimal CPU utilization.

Evolution Processing in AS6 Timeline

Release	Key Features
AR 6.1	Multicore platform for mapp packages, Automation Runtime API
AR 6.3	Multicore diagnostics (Profiler, SDM)
AR 6.4	Full multicore support for non-hard RT system tasks
AR 6.x	More to come e.g. mapp Track/IEC Task classes

Runtime Integration

Automation Runtime API enables system-level multicore control. RT Class-based task scheduling allows fine-grained priority management. Background tasks are dynamically distributed across cores.

Technology Package Multicore Support

Multicore support is integrated into several key packages:

• mapp View 6.1
• OPC UA FX 6.1
• OPC UA Client/Server
• mapp Robotics 6.2
• mapp Track (comming soon)

Tasks are automatically balanced across the least utilized cores, improving responsiveness and throughput. Tasks may be automatically migrated from one core to another at runtime based on system load.

OPC UA FX & OPC UA C/S 6.1

• Multicore Processing activated by default (configurable) – tasks balanced on least utilized cores

mapp View 6.1

• Multicore Processing activated by default - tasks balanced on least utilized cores

Real-World Example: mapp Robotics

Using Codian Delta Robots on APC3200:

• With multicore support, up to 7 robots can be handled simultaneously.
• CPU load is distributed across cores, significantly reducing bottlenecks on Core 0.
• Demonstrates scalability and efficiency of multicore task scheduling.

Diagnostics and Profiling

From AR 6.3 onwards:

• System Diagnostics Manager (SDM) and Automation Studio Profiler provide visibility into core usage.
• Developers can identify bottlenecks and optimize task distribution.

Hardware Compatibility

Not all B&R hardware supports multicore. BIOS settings and I/O system configurations may reserve cores. Refer to System Datasheets for supported targets and configurations.

Case Studies

• IO scheduler can not benefit from multicore processing
• Task classes parallelization will come in one of upcoming AR version

Unsuitable Project (AR 6.4)

High cyclic load (44.38%) not parallelizable. Only 12.4% of tasks could benefit from multicore. Minimal performance gain.

Suitable Project (AR 6.4)

45.5% of system tasks were multicore-ready. Real-world reduction of 30–40% in Core 0 load. Significant performance improvement.

Application Code Considerations

Pitfall: Priority-Based Synchronization

On single-core systems, task execution is serialized. On multicore systems, simultaneous access to shared memory can lead to race conditions.

Solution: Use memory locks or synchronization primitives (e.g., AsSem Standard Library) to ensure data integrity.

QnA

• How Multicore Processing is handled with a Hypervisor System?

  • Starting with AR 6.4 and AS 6.5 the Cores of an APC can be assigned to either GPOS or Automation Runtime

• Is debugger ready for that ? will the all cores be stopped if it reach a breakpoint in one core ??

  • Yes. The debugger stops tasks, not cores — tasks are stopped no matter which core they are running on

• Is ARsim also using multicore?

  • yes

• Does the “mappCNC” also support multicore processing (Since mappRobotics supports..)?

  • Yes

• Is multicore functionality supported on X20CP0410 and X20CP0411?

  • No, there is only a license for one core on these CPUs.

Configuration/additional info

OPCUA C/S : multicore enabling

MappMotion : Processing-> Symetric multiprocessing

[kovarj (Jaroslav Kovar)]

Where to find information if the PLC supports multicore? In the technical data table

As well as on our webpage, in the hardware details technical overview.

Example: https://www.br-automation.com/en-gb/products/plc-systems/x20-system/x20-plc/x20cp1686x/

[valerio.manenti]

@kovarj

Use memory locks or synchronization primitives (e.g., AsSem Standard Library) to ensure data integrity.

small note just to refresh our attention on this point.
Post was created 7 months ago, now we see more feedback every day about multi-core from our customers, and I have a feeling we didn’t put enough attention on using memory locks or synchronization primitives.
Great post
Ciao
Valerio

[kovarj (Jaroslav Kovar)]

Maybe you can publish new wiki article about it? Example, best way how to do it?

[Alexander_Jager (Alexander Jäger)]

Has this matter been dealt with? If so, where?

[kovarj (Jaroslav Kovar)]

Maybe @valerio.manenti you can update here. Im not in the story. I asked AI to generated me overview how this has been developed

Disclaimer, is AI generated overview. I think in general is valid, but I have no time to proof all facts

Consolidated change list (AR 6.1 → 6.5+):

• 6.1: multicore support introduced in AR stack; OPC UA components started using multicore execution.
• 6.1+: profiler gained multicore-awareness.
• 6.2: multicore scope extended further in motion/robotics stack (from support channel release material).
• 6.3: multicore diagnostics became operationally relevant (SDM/profiler usage in support flow).
• 6.4: larger system-level parallelization (hypervisor/core partitioning focus, non-hard-RT and comm workloads spread across cores).
• 6.5: SMP behavior became more explicit in mapp Motion route/robotics workloads; task/core assignment discussions became standard in cases.
• 6.5 known issues: debugger/profiler multicore handling and some configs/hardware combinations required fixes/workarounds.
• 6.6.x (latest observed in cases): multicore behavior still hardware-dependent (e.g., APC3100 handling changed over versions).

[valerio.manenti]

Disclaimer, is AI generated overview. I think in general is valid, but I have no time to proof all facts

well today I asked AI 4 questions, but how to said it was not lucky day for the answers.

good reference for multicore (Corne Geerts) Multi-core support since AS\AR V6.1 - Share Info & Ideas / How-To & Wikis - B&R Community

I don’t want to create confusion but there are few components, not only Automation Runtime, involved on Multi-core:
Automation Studio + Automation Runtime + mapp Motion + CPU hw upgrade.

6.1: multicore support introduced in AR stack; OPC UA components started using multicore execution.

Correct

6.1+: profiler gained multicore-awareness.

Multicore platform for mapp packages, Automation Runtime API

6.2: multicore scope extended further in motion/robotics stack (from support channel release material).

correct + you need to install at least mapp Motion 6.2. With symmetric multiprocessing enabled, the background tasks of the path planning are distributed across the available cores (this includes the velocity planning, workspace monitoring, and parts of the geometry planning.

6.3: multicore diagnostics became operationally relevant (SDM/profiler usage in support flow).

Correct, Multi-core diagnostics (Profiler, SDM):

6.4: larger system-level parallelization (hypervisor/core partitioning focus, non-hard-RT and comm workloads spread across cores).

1. Multi-core support for low priority AR-Core tasks & asynchronous standard libraries
2. Multi-core Support for ANSL communication: the system tasks related to ANSL communication are executed in parallel on all available processor cores.

6.5: SMP behavior became more explicit in mapp Motion route/robotics workloads; task/core assignment discussions became standard in cases.

SMP has been introduced on ACOPOStrak applications + we need to install mapp Motion 6.5 too.

For sure since AR 6.5 big news: Configuration option for assigning task classes to cores:

6.5 known issues: debugger/profiler multicore handling and some configs/hardware combinations required fixes/workarounds.

Regarding multicore, well, for sure AR and AS R&D are not bored at all , we have reported issues and some of them are already fixed on AR 6.6, AR 6.7, and we will see next week with new AS 6.7 release.

6.6.x (latest observed in cases): multicore behavior still hardware-dependent (e.g., APC3100 handling changed over versions).

I have to check, so far I have installed prj made with AS 6.5 and AR 6.5 on APC3100.

=================
My notes:

1. Regarding the hw now it’s documented (in clear way ) if the hw supports Multi-core:

2. We are learning more everyday on multi-core and I would like to mention, in particular for US team, Austin Carpenter and Adam Wagie for all their Support to application/Support and Sales team.

3. Last but not least, from our Academy we have a (free) New add-on online course: Multicore processing.

Ciao
Valerio

[valerio.manenti]

We have an update for AS 6.6 regarding Multi-core: Cache allocation for real-time optimization

Cache allocation can be used to reserve part of the last-level cache for a real-time task class and all higher-priority tasks. The simultaneous use of this cache can result in increased memory access times, particularly in systems with multiple processor cores. Cache allocation reserves a specific cache area exclusively for hard real-time tasks, which improves the determinism of execution times and reduces the risk of sporadic cycle time violations (cache Allocation is disabled for default).

Example with X20 CPU:

I made a test with APC4100 and unfortunately I can’t enable that:

time for a question to R&D…

Answer from R&D:
Hypervisor must be off for this (and it needs a save before you see the CAT options):

I know what you are thinking? What about my poor hypervisor? Is there any plan to integrate in the next releases that feature on Hylervisor too?

Feedback from R&D:

Cache allocation is already used for HV even in 4.xx AR versions but you cannot configure it and it is handled by the hypervisor.It is now configurable for AR due to multi core support since the same issues could occur with cache usage by TC#2 than it was with cache usage by the GPOS.

Ciao
Valerio